Espressif Systems /ESP32-H2 /SPI2 /DOUT_MODE

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Interpret as DOUT_MODE

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DOUT0_MODE)DOUT0_MODE 0 (DOUT1_MODE)DOUT1_MODE 0 (DOUT2_MODE)DOUT2_MODE 0 (DOUT3_MODE)DOUT3_MODE 0 (DOUT4_MODE)DOUT4_MODE 0 (DOUT5_MODE)DOUT5_MODE 0 (DOUT6_MODE)DOUT6_MODE 0 (DOUT7_MODE)DOUT7_MODE 0 (D_DQS_MODE)D_DQS_MODE

Description

SPI output delay mode configuration

Fields

DOUT0_MODE

The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

DOUT1_MODE

The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

DOUT2_MODE

The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

DOUT3_MODE

The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

DOUT4_MODE

The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

DOUT5_MODE

The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

DOUT6_MODE

The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

DOUT7_MODE

The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

D_DQS_MODE

The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

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